Detailed explanation of the use of port (IO) and Module in chisel

The main content is extracted from: https://blog.csdn.net/qq_34291505/article/details/87880730 1, Port (similar to input and output in verilog) 1. Define port list Before defining a module, you must first define the port. The whole port list is defined by the method "io [T <: data] (iodef: T)". Generally, its parameter is an obj ...

Posted by PoohStix on Sun, 23 Jan 2022 11:47:56 +0100