Sword Finger Offer - Nine Degrees 1506 - Seek 1+2+3+...+n

Posted by hitman6003 on Thu, 15 Aug 2019 07:26:52 +0200

The article was reproduced from: http://www.pythonheidong.com/blog/article/2880/

Sword Finger Offer - Nine Degrees 1506 - Seek 1+2+3+...+n
2013-11-29 19:22
Title Description:

To find 1+2+3+...+n, it is required that the keywords and conditional judgment statements (A?B:C) such as multiplication and division, for, while, if, else, switch, case, etc. cannot be used.

Input:

The input may contain multiple test samples.
For each test case, enter an integer n (1<= n<=100000).

Output:

For each test case,
Output 1+2+3+...The value of + n.

Sample input:
3
5
Sample output:
6
15
Theme Analysis:
Given a positive integer n, with a range not exceeding 100000, sum 1 +... + n, that is, value n * (n + 1) / 2. However, multiplication, division and looping are not allowed.Note: Addition can be used.
Obviously, if loops are not allowed, either repeat them N times or recursively.Do not allow me to multiply and divide, just use bitwise operations to simulate multiply and divide.Although I haven't been exposed to Verilog and multiplier since graduation, I can't forget the design ideas I learned, otherwise my tuition will not be paid in vain.
Note the following two ways:
    x^a * x^b = x^(a + b)
(a[n] * x^n + a[n-1] * x^(n-1) +... + a[0]* (b[m] * x^m + b[m-1] * x^(m-1) +... + b[0]) = multiply two by one large stack
Since binary operation is so convenient in a computer, we can expand a number by binary: 14 = 2^3 + 2^2 + 2^1, so two numbers are symmetrical and multiplied by two polynomials with x=2.
Next, 2 ^a * 2 ^b = 2 ^ (a + b) = 1 < < (a + b)
With this idea in mind, let's consider the integers a * b. If A and b are both 32-bit integers, then the sum of the product of all the binary bits of a and b is the same.Now refer to the general writing in Verilog:
First Layer "Cycle", fun1():
    fun1(0);
    fun1(1);
    ...
    fun1(31);
  
The second level loop calls more than one fun2() in fun1:
    fun2(0);
    fun2(1);
    ...
    fun2(31);
There is a reason why Verilog does not recommend for-loop. After all, the circuit design and writing software are different. The specific reason can be Baidu "Verilog for".However, this kind of writing can really avoid the use of loops and meet the requirements of interview questions.
There are two last points:
1. The range of n in the title does not exceed 100,000, so no more than 17 digits in binary digits and 17 digits in loop is enough.
2. Result range can obviously exceed int range, use long long int.
 1 // 653472    zhuli19901106    1506    Accepted    Click here to view all case Execution results    1020 KB    1606B    50MS
 2 // 201311190134
 3 #include <cstdio>
 4 using namespace std;
 5 
 6 void add2(long long int &x, long long int &y, int i, int j, long long int &res)
 7 {
 8     res += (((!!(x & (1 << i))) & (!!(y & (1 << j)))) << (i + j));
 9 }
10 
11 void add1(long long int &x, long long int &y, int i, long long int &res)
12 {
13     add2(x, y, i, 0, res);
14     add2(x, y, i, 1, res);
15     add2(x, y, i, 2, res);
16     add2(x, y, i, 3, res);
17     add2(x, y, i, 4, res);
18     add2(x, y, i, 5, res);
19     add2(x, y, i, 6, res);
20     add2(x, y, i, 7, res);
21     add2(x, y, i, 8, res);
22     add2(x, y, i, 9, res);
23     add2(x, y, i, 10, res);
24     add2(x, y, i, 11, res);
25     add2(x, y, i, 12, res);
26     add2(x, y, i, 13, res);
27     add2(x, y, i, 14, res);
28     add2(x, y, i, 15, res);
29     add2(x, y, i, 16, res);
30     add2(x, y, i, 17, res);
31     add2(x, y, i, 18, res);
32     add2(x, y, i, 19, res);
33 }
34 
35 int main()
36 {
37     long long int n;
38     long long int res;
39     long long int x, y;
40     
41     while(scanf("%lld", &n) == 1){
42         res = 0;
43         x = n;
44         y = n + 1;
45         add1(x, y, 0, res);
46         add1(x, y, 1, res);
47         add1(x, y, 2, res);
48         add1(x, y, 3, res);
49         add1(x, y, 4, res);
50         add1(x, y, 5, res);
51         add1(x, y, 6, res);
52         add1(x, y, 7, res);
53         add1(x, y, 8, res);
54         add1(x, y, 9, res);
55         add1(x, y, 10, res);
56         add1(x, y, 11, res);
57         add1(x, y, 12, res);
58         add1(x, y, 13, res);
59         add1(x, y, 14, res);
60         add1(x, y, 15, res);
61         add1(x, y, 16, res);
62         add1(x, y, 17, res);
63         add1(x, y, 18, res);
64         add1(x, y, 19, res);
65         res >>= 1;
66         printf("%lld\n", res);
67     }
68 
69     return 0;
70 }

 

The article was reproduced from: http://www.pythonheidong.com/blog/article/2880/

Topics: Verilog