Programmer Think

tinyriscv, the core cpu part of SoC project, is designed with the classic three-stage pipeline structure, which is well-known: value - > decoding - > execution three-stage pipeline. The execution module was annotated in the previous blog post. Now let's introduce the interrupt module: catalogue 1. Interrupt structure diagram 2. csr_re ...

Basic circuit 1-bit full adder module full_adder( input a, input b, input cin, output sum, output cout ); assign {cout,sum}=a+b+cin; endmoudle abcinsumcout0000000110010100110110010101011100111111 module full_adder( input a, input b, input cin, output sum, output cout ); assign sum=a^b^cin; assign cout=(a&b) |(c ...

The creation of UV M is inseparable from the three core elements of factory: registration, creation and coverage `uvm_{component,object}_utils() uvm_{component,object}::type_id::create() uvm_{type,inst}_override{,_by_type}() Among them, override instance program: override method set by type_ type_ Override to illustrate. module factory_ove ...

preface Verilog, Xilinx ISE 13.4, BASYS2, modulo 60 counter 1, Development environment Verilog language 1. Data type Constant: parameter IN_width = 4；Can be used to define variable width Variable: wire Type: use assign Assignment; Input / output signal default reg Type: in always Internal assignment; Indicates the trigger out ...

1, Experimental principle 1. Single cycle CPU Single cycle CPU can be regarded as composed of data path and control unit. Data path refers to the path through which data passes and the functional components involved in the path during the execution of instructions. The control unit generates different control signals for different data ...

1. Tasks A four digit simple calculator is designed. The number keys are input by the matrix keyboard and the display is output by the four digit nixie tube. The four operations of +, -, *, / can be realized correctly (regardless of the operation of decimals). 2. System block diagram It is mainly composed of five modules, namely matrix keybo ...

Create project Find a place to create a new folder, set the path of this project to that folder, and the project name can be taken by yourself (in order to avoid inconsistency later, it is recommended to take the same as me) Create from empty project No files need to be added Select the development board, I choose this, and then nex ...

WeChat official account: FPGA power alliance Blogger micro signal: fpga_start WeChat official account link: generate block of verilog Previous posts introduced the concepts of functions, tasks, macro definitions and parameters that can be used to simplify and optimize logical code. Today's blog introduces the synthesizer of simplified circui ...

Article catalog Experiment 1: project creation, compilation and download Experiment 2: FPGA decoder combinational logic Experiment 3: counter waveform simulation and signalTap Experiment 4: time reference circuit and multi period counter with Enable Experiment 5: multi cycle shift register circuit Experiment 6: counter, ROM and DDS Expe ...

1. Introduction The content of this article is my summary of the process of learning Verilog HDL grammar. My expectation is to write the content in detail, but as a beginner, it is inevitable to make mistakes or logical problems, so I will revise, adjust and supplement the content for a long time. First, what is Verilog? Is a Hardware Des ...