HDLbits question brushing series 2-Verilog/Procedure & More features
summary
This section mainly exercises the basic grammar of verilog.
Schematic diagram + code + simulation screenshot Alwaysblock1
There are two types of composite awlays modules that can be integrated:
always @(*)； The variable processed inside is reg, and the overall function is equivalent to the assign statement. The assign state ...
Posted by Skyphoxx on Mon, 20 Sep 2021 08:37:55 +0200