dpdk network card queue initialization + receiving and contracting
ixgbe_dev_rx_queue_start set dma address
IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
recv
{
rxdp = &rx_ring[rx_id];
/* If the DD written back by the network card is 0, the loop will jump out */
staterr = rxdp->wb.upper.statu ...
Posted by johnie on Sat, 29 Jan 2022 06:20:31 +0100
Chapter 2 Cache and memory
This blog is a brief note of DPDK in simple terms
2.1 introduction to storage system
For packet processing, there are mainly two parts (personal understanding), one is CPU The other is CPU Scheduling of instructions and data to be processed. How to give full play CPU On the basis of performance Cache，Memory, SATA Disk, PCIe Devices (network ...
Posted by dbradbury on Mon, 08 Nov 2021 11:29:28 +0100