UVM_ Overlay instance
The creation of UV M is inseparable from the three core elements of factory: registration, creation and coverage
`uvm_{component,object}_utils()
uvm_{component,object}::type_id::create()
uvm_{type,inst}_override{,_by_type}()
Among them, override instance program: override method set by type_ type_ Override to illustrate.
module factory_ove ...
Posted by john_6767 on Wed, 02 Mar 2022 08:33:38 +0100
System Verilog - Fundamentals of object-oriented programming
1, Overview of classes
Handle (spatial pointer) Object (storage space)
Transaction t1, t2;//Declare handle t1, t2
t1 = new();//Instantiate the object and assign its handle to t1
t2 = t1;//Assign the value of t1 to t2, that is, t1 and t2 point to the same object
t1 = new();//Instantiate the second object and give its handle to t1
//At thi ...
Posted by Trizen on Fri, 18 Feb 2022 20:03:47 +0100
System Verilog - data type
1, Built in data type
Four valued logic typeBinary logic typelogic integer reg net-typebyte int longint shortint bit
Signed typeUnsigned typebyte integer int longint shortintlogic bit reg net-type
Tips: (1) The default value returned by four value status is x, and the default value returned by two value status is 0. (2) logic type can onl ...
Posted by teamfox20 on Tue, 15 Feb 2022 12:32:26 +0100
QuartusII and Modelsim joint simulation to realize a simple multiplier without clock signal
Create project
Find a place to create a new folder, set the path of this project to that folder, and the project name can be taken by yourself (in order to avoid inconsistency later, it is recommended to take the same as me)
Create from empty project
No files need to be added
Select the development board, I choose this, and then nex ...
Posted by starphp on Mon, 31 Jan 2022 23:47:10 +0100
Developing FPGA under linux
For more sharing, please visit my personal blog
https://www.niuiic.top/
This paper introduces how to develop FPGA under linux.
compiler
Due to the particularity of FPGA, only commercial ides can be competent for the whole development process. Therefore, there is no need to find open source alternative products. It is most appropriate to dir ...
Posted by Brian Swan on Sun, 30 Jan 2022 07:03:02 +0100
SV small project - simple verification environment construction of asynchronous fifo (full)
catalogue
0. Preface
1. Overall environment construction
1.1 interface construction
1.2 clk generator setup
1.3 rst generator setup
1.4 environment construction
1.5 # top construction
1.5.1 fifo_top build
1.5.2 top floor construction
2. Add remaining components
2.1 transaction component
2.2 generator components
2.3 driver assembly ...
Posted by (RL)Ian on Thu, 27 Jan 2022 00:50:58 +0100
SV Chapter 3 procedure statements and subroutines
In fact, when writing design or verification, the code basically unloads tasks or functions. This chapter mainly introduces the improvement of SV like C language - processing parameter cases.
3.1 procedure statement
Loop variables are defined in the for loop, and the scope is limited to the inside of the loop to avoid some code vulnerabil ...
Posted by bitman on Sun, 23 Jan 2022 17:52:16 +0100
SV Chapter 2 data types
2.8 select storage array type
This paper introduces some criteria for selecting storage types based on flexibility, memory usage, speed and sorting requirements.
2.8.1 flexibility
If the index of an array is a continuous nonnegative integer, a fixed width or dynamic array should be used.If the fixed width array has been selected when the ...
Posted by Marchingknight11 on Sun, 23 Jan 2022 11:30:21 +0100
User defined and enumerated data types
User defined and enumerated data types
1. User defined type
The user-defined type keyword is typedef, for example
typedef int unsigned uint; //unit is a custom data type
unit a, b; //Declare two variables with a custom data type
Look at an example
module type1_tb;
typedef bit bit_t; //Customize a bit_ Tdata type
bit_t a = 0;
...
Posted by itsgood on Tue, 21 Dec 2021 08:02:28 +0100
System Verilog notes Procedure statements and subroutines
Chapter III procedure statements and subroutines
1. Procedure statement
sv absorbs some features of C + +, including break and continue statements.
//for loop statements and do... while statements
initial begin:example //You can give this initial a number and name, which is called example here
integer a[10],sum,j;
fo ...
Posted by jhenary on Mon, 20 Dec 2021 01:22:40 +0100