5, RISC-V kernel structure - interrupt:
tinyriscv, the core cpu part of SoC project, is designed with the classic three-stage pipeline structure, which is well-known: value - > decoding - > execution three-stage pipeline.
The execution module was annotated in the previous blog post. Now let's introduce the interrupt module:
catalogue
1. Interrupt structure diagram
2. csr_re ...
Posted by MissiCoola on Mon, 07 Mar 2022 03:12:12 +0100
3, RISC-V kernel architecture - Execution:
tinyriscv, the core cpu part of SoC project, is designed with the classic three-stage pipeline structure, which is well-known: value - > decoding - > execution three-stage pipeline.
The decoding module was annotated in the last blog post. Now let's introduce the execution module:
catalogue
1. Annotation of execution module
2. ex.v (co ...
Posted by musclehead on Sun, 06 Mar 2022 09:34:51 +0100
The UVM Primer-Chapter1: Introduction and DUT
1. Introduction
The UVM Primer is an introductory book on UVM, written and published by Ray Salemi. It is a free and open source project. The code can be downloaded from GitHub. This book is only more than 100 pages long. It is a step-by-step in-depth study around TinyALU. It is very suitable for beginners of UVM. Of course, it also needs to ...
Posted by nick5449 on Sat, 05 Feb 2022 03:48:15 +0100
Full record of terminal Caton optimization
Introduction: at present, the performance of mobile phone SOC is less and less. Many programmers do not pay much attention to performance optimization in the development of terminal programs, especially alignment and branch optimization. However, once these two problems occur, they are very hidden and difficult to check, However, fortunately, w ...
Posted by pedro84 on Mon, 08 Nov 2021 04:42:25 +0100