Assertion assertion introduction 2-sequence
1.sequence basic operation symbols
Symbolmeaning##Symbol used to indicate periodic delay
1.##n Indicates in n After two clock cycles,##0 means in the current cycle, i.e. overlapping cycle
//One cycle after a is pulled up, b is also pulled up
sequence a_b
@(posedge clk) a ##1 b
endsequence
2.##[min:max] indicates the clock cycle delay with ...
Posted by ADLE on Tue, 22 Feb 2022 16:50:51 +0100
The UVM Primer-Chapter1: Introduction and DUT
1. Introduction
The UVM Primer is an introductory book on UVM, written and published by Ray Salemi. It is a free and open source project. The code can be downloaded from GitHub. This book is only more than 100 pages long. It is a step-by-step in-depth study around TinyALU. It is very suitable for beginners of UVM. Of course, it also needs to ...
Posted by nick5449 on Sat, 05 Feb 2022 03:48:15 +0100
Introduction to the use of uvmgen and its UVM environment
preface
UVM is a methodology of IC Verification. The basic framework of verification environment built by UVM is similar. Therefore, the basic framework of verification environment of UVM can be generated through script. This paper mainly introduces a script uvmgen provided by synopsys in vcs tool. Through this script, a complete set of ...
Posted by cyball on Mon, 24 Jan 2022 14:47:07 +0100
Synchronous communication (event) - UVM
1, event
1.1 differences between event in UVM and event in SV
The difference between event in UVM and event in SV is that the same object is mainly IPC in SV. UVM is not limited to one object. In order to solve the synchronization problem of different component threads, it also needs to maintain the closure of UVM. Therefore, it establish ...
Posted by homer.favenir on Sun, 16 Jan 2022 09:13:21 +0100
sequence of UVM learning notes
1. Why use sequence
The main function of sequence is to facilitate the generation of transactions for testing. It is unreasonable to directly generate a transaction in the driver during verification. The reasons include:
The function of the driver is to convert the transaction into an excitation signal. If the function generating the transact ...
Posted by exasp on Sat, 04 Dec 2021 21:34:58 +0100
(19) Summary of the strongest sequence related macro operations in the history of UVM
Summary of the strongest sequence related macro operations in history
1, Sequence macro
The following code is a natural code description of the execution process of the start() method. You can see the sequence relationship and conditions of their execution:
sub_seq.pre_start() (task)
sub_seq.pre_body() (task) if call_pre_pos ...
Posted by the_ut_tick on Fri, 19 Nov 2021 02:04:16 +0100