RISC CPU design based on Verilog

Abstract: in fact, in the design of a CPU, each sub module is relatively basic and simple, but the combined overall architecture will be more complex, whether it is timing path, data path and control path. Here, we mainly introduce the sub modules of the whole microarchitecture in detail. 1. PC fetch, PC branch, instruction jump and L2 stack ...

Posted by Dujo on Sun, 10 Oct 2021 04:17:27 +0200