Programmer Think

catalogue Foreword 3.2.3.1 4-bit Shift Register(shift4) Solution: 3.2.3.2 Left/right rotator(rotate100) Solution: 3.2.3.3 Left/right arithmetic shift by 1 or 8(shift18) Solution: 3.2.3.4 5-bit LFSR(Lfsr5) Solution: 3.2.3.5 3-bit LFSR(Mt2015 lfsr) Solution:  3.2.3.6 32-bit LFSR(Lfsr32) Solution: 3.2.3.7 shift register(Exams/m ...

Book "the art of hardware architecture: design methods and technologies of digital circuits" (1) Metastable state 1.1 concept Caused by violation of the set-up time and hold time of the trigger In the window of the rising edge of the clock, the data changes and the output is unknown or metastable Metastable window Me ...

Write in front Write a new pit: recommend a very good website for practicing Verilog. There are one or two hundred questions, which basically covers all aspects of Verilog grammar. It is a very good introductory learning website. Website connection: HDLBits The questions are all done by ourselves. They are the correct answers that have been v ...

1, Principle of state machine State machine (FSM), also known as finite state machine One stage state machine The one-stage state machine seems to solve all logic (including input, output and state) in one always. This writing method seems very concise, but it is often not conducive to maintenance. This writing method is not recommended, b ...

Experiment Name: electronic organ design - task 2 (for learning purposes only, please indicate the source) 1, Experimental circuit diagram, state diagram, flow chart, program code, simulation code and simulation waveform diagram (only core function code can be written, and the code shall be annotated) 1. Design idea Selections: The design bas ...

Problem background Today, I encountered a problem when writing uart serial port code and simulating. Two signals send in uart module_ EN and tx_state. The original expectation was send_en a clock high level appears, TX_ The high state indicates that the serial port is transmitting data. The code is as follows: //tx_state signal alway ...

Abstract: in fact, in the design of a CPU, each sub module is relatively basic and simple, but the combined overall architecture will be more complex, whether it is timing path, data path and control path. Here, we mainly introduce the sub modules of the whole microarchitecture in detail. 1. PC fetch, PC branch, instruction jump and L2 stack ...

preface On weekdays, blog posts are long or slightly long, but recently I feel that this is not conducive to reading or writing? It's not conducive to writing. It's easy to understand that everyone has their own formal career, goes to work or goes to school, and doesn't have the overall time to write articles. This will lead to a break like ...