Programmer Think

tinyriscv, the core cpu part of SoC project, is designed with the classic three-stage pipeline structure, which is well-known: value - > decoding - > execution three-stage pipeline. The execution module was annotated in the previous blog post. Now let's introduce the interrupt module: catalogue 1. Interrupt structure diagram 2. csr_re ...

tinyriscv, the core cpu part of SoC project, is designed with the classic three-stage pipeline structure, which is well-known: value - > decoding - > execution three-stage pipeline. The decoding module was annotated in the last blog post. Now let's introduce the execution module: catalogue 1. Annotation of execution module 2. ex.v (co ...

preparation: patienceA cup of coffeeA board and a serial port debugging line, at least 16G SD card of any brand  A Linux distribution that can operate skillfully (Archlinux or Ubuntu is recommended)Learn about how to use qemu and binfmt to create RISC-V simulation running environment Recommended readingGet a general idea of how to create a blo ...

Load instruction Instruction name function ISA type usage meaning LA Address loading, pseudo instruction RV32I/RV64I  Pseudo instruction la rd, symbol Load the address of the symbol into x[rd]. When compiling location independent code, it is extended to the global offset table (Global Offset Table). For RV32I, it is equivalent to ex ...

Chitu V307 (CH32V307) is a RISC-V core MCU, which is equipped with qinheng self-developed RISC-V core highland barley V4F, with a maximum dominant frequency of 144MHz and supports single precision floating-point operation (FPU). Generally, the size of Flash is 256 KB and the size of SRAM is 64 KB. After carefully reading the application manu ...

[reference] environment deployment - rcore tutorial deploy - gitbook: https://rcore-os.github.io/rCore-Tutorial-deploy/docs/pre-lab/env.html [reference] experimental environment configuration - rCore-Tutorial-Book-v3 0.1 document: https://rcore-os.github.io/rCore-Tutorial-Book-v3/chapter0/5setup-devel-env.html [reference] qemu/qemu: Official QE ...

Catalogue of series articles (1) Designing RISC-V processor from scratch -- instruction system (2) Design RISC-V processor from scratch -- Design of single cycle processor (3) Designing RISC-V processor from scratch -- Simulation of single cycle processor (4) Designing RISC-V processor from scratch -- Optimization of ALU preface In ...

background As we all know, one of the core functions of the operating system is task scheduling. By switching a CPU core between multiple executable tasks, the task scheduler can realize that multiple tasks share one or more CPU cores, so as to maximize the use of CPU core resources. At the same time, through fast task switching, users can fee ...

Author: bigbat 1, Introduction W800 wifi chip is integrated in ch2601 development board. This chip is a complete mcu chip. Theoretically, there is no need for the main chip of ch2601 to worry about network communication. Just send instructions and data to w800. Ch2601 interacts with w800 chip through SPI bus and communicates with AT command ...

After the previous toss, we have designed our own test development board and built a development environment, Then the functional test is officially started. The test sequence starts from simple, step by step preface The following ESP32-C3 function tests are based on the development board designed by ourselves: Draw an ESP32-C3 development ...