Programmer Think

1, Introduction to AXI 1.AXI overview ZYNQ closely combines high-performance ARM Cotex-A series processors with high-performance FPGA in a single chip. After integrating processors with different process characteristics and FPGA on one chip, the interconnection path between on-chip processor and FPGA has become the top priority of ZYNQ ch ...

Verilog realizes serial communication (UART) This code refers to the relevant tutorials of wildfire to realize the sending and receiving loop. At the same time, the LED light can be controlled on and off through the serial port data. When the computer sends data, it is necessary to select the HEX sending mode and send hexadecimal data for cont ...

catalogue Foreword 3.2.3.1 4-bit Shift Register(shift4) Solution: 3.2.3.2 Left/right rotator(rotate100) Solution: 3.2.3.3 Left/right arithmetic shift by 1 or 8(shift18) Solution: 3.2.3.4 5-bit LFSR(Lfsr5) Solution: 3.2.3.5 3-bit LFSR(Mt2015 lfsr) Solution:  3.2.3.6 32-bit LFSR(Lfsr32) Solution: 3.2.3.7 shift register(Exams/m ...

catalogue 1. Theoretical introduction 2. Architecture design 3. Code design 1, Send module code 2, Receiving code design 3, Top level module design IV. test code 4. Simulation experiment 1. Theoretical introduction uart: Universal Asynchronous Receiver / transmitter, which is a serial transceiver. Since there is no clock, both partie ...

Book "the art of hardware architecture: design methods and technologies of digital circuits" (1) Metastable state 1.1 concept Caused by violation of the set-up time and hold time of the trigger In the window of the rising edge of the clock, the data changes and the output is unknown or metastable Metastable window Me ...

Write in front Write a new pit: recommend a very good website for practicing Verilog. There are one or two hundred questions, which basically covers all aspects of Verilog grammar. It is a very good introductory learning website. Website connection: HDLBits The questions are all done by ourselves. They are the correct answers that have been v ...

Experiment Name: electronic organ design - task 2 (for learning purposes only, please indicate the source) 1, Experimental circuit diagram, state diagram, flow chart, program code, simulation code and simulation waveform diagram (only core function code can be written, and the code shall be annotated) 1. Design idea Selections: The design bas ...

Write in front         In AXIS, we packaged the IP of two axi4 stream interfaces (one master and one slave)( Take you to a quick start AXI4 bus -- AXI4 stream (2) -- Xilinx AXI4 stream interface IP source code simulation analysis ), the two IPS are simulated and analyzed, and the code provided by XILINX is also studied. In ...

Summary of the strongest sequence related macro operations in history 1, Sequence macro The following code is a natural code description of the execution process of the start() method. You can see the sequence relationship and conditions of their execution: sub_seq.pre_start() (task) sub_seq.pre_body() (task) if call_pre_pos ...

Problem background Today, I encountered a problem when writing uart serial port code and simulating. Two signals send in uart module_ EN and tx_state. The original expectation was send_en a clock high level appears, TX_ The high state indicates that the serial port is transmitting data. The code is as follows: //tx_state signal alway ...