Verilog, Xilinx ISE 13.4, BASYS2, modulo 60 counter
1, Development environment
1. Data type
Constant: parameter IN_width = 4；Can be used to define variable width
Variable: wire Type: use assign Assignment; Input / output signal default
reg Type: in always Internal assignment; Indicates the trigger out ...
Posted by realestninja on Sun, 27 Feb 2022 09:00:41 +0100
The whole blog is a correction book at the end. The code is all right and can be simulated normally
1. Introduction to FIFO
2. Synchronous FIFO
A clock is used for reading and writing
Module block diagram Port introduction:
sys_clk: 50MHz system clocksys_rst_n: System reset, low effectivewr_e ...
Posted by teebo on Fri, 11 Feb 2022 01:54:08 +0100
1, Introduction to HLS
HLS is High level Synthesis It compiles c or c + + language into RTL level language that FPGA can read and run Comparison with VHDL or verilog Advantages: use high-level language to complete the functions expected to be realized on the hardware circuit, which is more abstract and easy to implement. Disadvantages: Alt ...
Posted by tmharrison on Wed, 09 Feb 2022 11:31:21 +0100
For more sharing, please visit my personal blog
This paper introduces how to develop FPGA under linux.
Due to the particularity of FPGA, only commercial ides can be competent for the whole development process. Therefore, there is no need to find open source alternative products. It is most appropriate to dir ...
Posted by Brian Swan on Sun, 30 Jan 2022 07:03:02 +0100
Experiment 1: project creation, compilation and download
Experiment 2: FPGA decoder combinational logic
Experiment 3: counter waveform simulation and signalTap
Experiment 4: time reference circuit and multi period counter with Enable
Experiment 5: multi cycle shift register circuit
Experiment 6: counter, ROM and DDS
Posted by TRemmie on Wed, 19 Jan 2022 04:30:42 +0100
1, Experimental purpose
Master the programming and use of finite state machine.
2, Experimental content
An intersection traffic light controller is designed. There are red lights, yellow lights and green lights in the East-West (b) and North-South (a) directions, with durations of 45, 5 and 40 seconds respectively. Its function is verifi ...
Posted by decessus on Sun, 16 Jan 2022 20:41:23 +0100
1, Introduction to AXI
ZYNQ closely combines high-performance ARM Cotex-A series processors with high-performance FPGA in a single chip. After integrating processors with different process characteristics and FPGA on one chip, the interconnection path between on-chip processor and FPGA has become the top priority of ZYNQ ch ...
Posted by dannymc1983 on Thu, 13 Jan 2022 05:22:14 +0100
This year, the South China competition area is over, and there are still more than 20 days for the national competition, which can be regarded as a few days of leisure. I have a special feeling for Lora. I have been using it since the last Jichuang competition. At first, I was always attached to the WiFi module, but the WiFi ...
Posted by rrijnders on Mon, 03 Jan 2022 23:06:42 +0100
Verilog realizes serial communication (UART)
This code refers to the relevant tutorials of wildfire to realize the sending and receiving loop. At the same time, the LED light can be controlled on and off through the serial port data. When the computer sends data, it is necessary to select the HEX sending mode and send hexadecimal data for cont ...
Posted by tasistro on Thu, 30 Dec 2021 21:51:46 +0100