RISC CPU design based on Verilog

Abstract: in fact, in the design of a CPU, each sub module is relatively basic and simple, but the combined overall architecture will be more complex, whether it is timing path, data path and control path. Here, we mainly introduce the sub modules of the whole microarchitecture in detail. 1. PC fetch, PC branch, instruction jump and L2 stack ...

Posted by Dujo on Sun, 10 Oct 2021 04:17:27 +0200

Do you need to explicitly use IBUF and OBUF like primitives in logic design?

preface On weekdays, blog posts are long or slightly long, but recently I feel that this is not conducive to reading or writing? It's not conducive to writing. It's easy to understand that everyone has their own formal career, goes to work or goes to school, and doesn't have the overall time to write articles. This will lead to a break like ...

Posted by Jaxolotl on Sun, 19 Sep 2021 19:21:59 +0200